1. Field of the Invention
The present invention relates to the field of semiconductor memories, and more specifically, to a semiconductor random access memory with large-signal I/O lines routed over the small-signal region of the memory.
2. Description of Related Art
In modern complex integrated circuits the layout of the various components or logical blocks of the circuit is extremely important. The goal is to use, as efficiently and as economically as possible, the limited amount of silicon area available on a die. This implies that silicon area is mainly used for active devices and components and not for interconnections or signal line routing. Another goal in circuit layout design is to improve circuit performance by placing and orienting those logical components next to each other which frequently interact with one another.
Microprocessor integrated circuit design is one application where circuit layout is very important. Microprocessors are comprised of many discrete units such as multipliers, adders, registers, bus controllers, and "on chip" memories or caches, etc. The positioning and orientation of these blocks relative to one another is important for overall microprocessor performance and circuit packing density. One of the largest consumers of silicon area in a microprocessor is the "on chip" cache or memory. As microprocessors become more and more complicated the size and performance requirements of "on chip" memories or caches are increasing.
There have been a couple of different layout schemes proposed for the layout of large on chip caches. One scheme, shown in FIG. 1, simply adds more rows to the array. A problem with this technique, however, is that as more rows are added to the array the bit-lines which access a column of cells become larger. As bit-lines become longer, access speeds decrease and device performance suffers. In an attempt to solve the problem of excessively long bit-lines and resulting poor performance, large memory arrays having a "butterfly" configuration, as shown in FIG. 2, have been proposed. This technique places the Sense-Amps and the Input/Output logic of the array at the center of the array, and forms two smaller arrays on either side of the I/O logic. The bit-line lengths in this configuration are only half as long as similar size memory arrays. This configuration increases the speed performance of the array. Unfortunately, however, in order to interconnect the I/O lines to the I/O logic at the center of the array, the I/O lines are routed around the side of the array. This technique consumes an unacceptable amount of silicon area, which in modern high-density integrated circuits is better used to form active devices than for routing I/O lines to the array.
Thus, what is desired is a novel layout for a large memory array which efficiently utilizes the available silicon area for the array, which has good performance, and which allows a circuit designer a great deal of freedom in choosing a layout for the array and a layout for the logical components coupled to the array.